Citi: "Tao's Law" Signals Shift Toward Chip/Circuit/System Design Innovation; Advanced Packaging Players Such as ASMPT (00522.HK) Expected to Benefit - AASTOCKS.com

Citigroup's report highlights that Huawei's 'Tao's Law', unveiled at the IEEE ISCAS conference, marks a paradigm shift in chip design philosophy, moving away from traditional geometric scaling toward ... Read original →

Huawei’s 'Tao’s Law' isn’t a stopgap—it’s a strategic pivot away from Moore’s Law under U.S. tech sanctions. By leveraging LogicFolding and 1.5µm-pitch hybrid bonding to stack logic, analog, and memory vertically, Huawei achieves 238 million transistors/mm² without EUV, effectively substituting system-in-package (SiP) architecture for node scaling. This triggers cascading demands: EDA vendors must overhaul 3D-aware design flows, while SMIC and Hua Hong accelerate non-EUV interconnect innovations. Geopolitically, Washington may restrict hybrid bonding tools, raising supply chain friction. TSMC and Samsung, despite superior 3D-IC capabilities, remain tethered to costly EUV front-end processes—making Huawei’s approach surprisingly agile. Within 18 months, ASMPT and other advanced packaging enablers will dominate the bottleneck layer. If validated in AI accelerators, this vertical paradigm could redefine global chip design philosophy.