JEDEC releases new SPHBM4 standard to slash AI memory costs

JEDEC has released the new SPHBM4 standard aimed at significantly reducing the cost of high-bandwidth memory (HBM), which is currently extremely expensive and used in the fastest AI processors. While ... Read original →

JEDEC’s SPHBM4 standard strategically trades latency for a fundamental reshaping of AI memory economics. Technically, it pushes SerDes and FEC into the PHY layer, compelling IP vendors to accelerate low-power, multi-channel DDR controller development while eroding the pricing power of advanced packaging like CoWoS. For TSMC in Taiwan, China, near-term impact is muted—its HBM4E+CoWoS stack still dominates premium AI chips—but cost-sensitive training clusters could force reallocation of its 3nm capacity. U.S., Japanese, and Korean DRAM makers face compatibility risks: SPHBM4’s fixed 0.75V I/O may clash with existing process nodes, threatening yields. Samsung and SK Hynix will likely counter with 'HBM4 Lite' variants rather than full adoption. Over the next 18 months, SPHBM4 won’t displace HBM4 but will enable second-tier AI chipmakers to carve niches and pressure JEDEC to embed cost-aware design into HBM5.