AI is starting to out-design chip engineers in narrow areas as LLMs accelerate software chip design tool development — "There is still a lot of human guidance" says Berkley researcher - Tom's Hardware

As Large Language Models (LLMs) advance, artificial intelligence is beginning to outperform chip engineers in narrow design domains, particularly in accelerating the development of software chip desig... Read original →

AI surpassing human engineers in narrow chip design tasks signals EDA’s shift from assistive to directive. This will cascade into IP reuse, physical verification, and power optimization stacks, forcing Synopsys and Cadence to embed generative AI faster. Compliance risks rise: if AI-generated RTL contains hidden backdoors or violates export controls, liability ambiguity will inflate audit costs. TSMC and Samsung may tighten certification for third-party AI-driven design flows, reshaping supply chain trust. Strategically, NVIDIA could acquire AI-EDA startups (e.g., SambaNova affiliates) to close the loop via its AI infrastructure, while Intel might bundle AI design services into IFS to win clients. Within 12–24 months, 'human-AI co-design velocity' will replace transistor density as the key benchmark—triggering structural attrition in traditional front-end engineering roles.