ASE Launches Automated 310mm Panel-Level Packaging to Accelerate AI Innovation - 01net

ASE (Amkor Semiconductor Electronics) has launched automated 310mm panel-level packaging technology, marking a significant advancement in AI chip innovation. This breakthrough addresses the growing de... Read original →

ASE’s automated 310mm panel-level packaging (PLP) isn’t just a process upgrade—it’s a strategic leap to overcome AI chip physical bottlenecks. Technically, it pressures upstream substrate suppliers to deliver materials with superior thermal stability and lower dielectric loss, while forcing EDA vendors to adapt design rules for oversized panels—potentially accelerating the shift of Chiplet ecosystems from wafer- to panel-level. Geopolitically, though based in Taiwan, China, this capacity skirts immediate U.S. CHIPS Act restrictions but remains vulnerable if Washington tightens export controls on advanced packaging tools. In response, Amkor may double down on hybrid bonding with Intel, while JCET could push 280mm transitional solutions via SMIC in mainland China. Within 18 months, 310mm PLP will become the cost inflection point for AI accelerators: early-scale adopters will slash per-watt performance costs by over 15%, seizing pricing power in edge AI markets.