Cadence announces collaboration with Intel Foundry to accelerate Intel 14A process optimization for HPC and mobile designs - Manila Standard

On June 23, 2026, Cadence announced an expanded collaboration with Intel Foundry to accelerate optimization of Intel’s 14A process technology, particularly for high-performance computing (HPC) and mob... Read original →

The Cadence–Intel Foundry alliance on 14A isn’t just process tuning—it’s a strategic pivot to system-level scaling as Moore’s Law stalls. Technically, AI-driven DTCO tightens the EDA-fab feedback loop, pressuring TSMC and Samsung to open PDKs faster to retain design wins. Geopolitically, tightening U.S. export controls on advanced tools push Intel Foundry deeper into domestic EDA reliance, raising barriers for non-U.S. foundries seeking equivalent capabilities. Synopsys will likely counter by deepening its co-optimization with TSMC below 2nm, while Taiwan, China-based players risk losing HPC traction without access to next-gen AI-EDA flows. Within 18 months, such vertical integration will become table stakes—but at the cost of a more fragmented global semiconductor ecosystem, where efficiency gains are offset by structural supply-chain friction.