Cadence’s Anirudh Devgan to Present at BofA Conference - 01net

Cadence engineer Anirudh Devgan's presentation at the BofA conference highlights the semiconductor industry's growing emphasis on security verification. As cybersecurity threats intensify, chip securi... Read original →

Cadence’s spotlight on security verification at the BofA conference signals a paradigm shift: chip design is moving from performance-centric to security-by-construction. Technically, this forces EDA stacks to embed formal methods and hardware root-of-trust checks, compelling IP vendors and foundries like TSMC to overhaul DfS workflows. Regulatory pressure from upcoming U.S.-EU chip security mandates will raise compliance costs, putting Taiwan, China; mainland China; and Korean fabs at risk if they lack automated verification. Synopsys will likely fast-track integration of Verified Boot with AI-powered vulnerability detection, while Siemens EDA may leverage open-source frameworks to capture cost-sensitive clients. Within 18 months, security verification will become a mandatory pre-tapeout gate—especially for automotive and defense SoCs—where designs lacking third-party certification face market exclusion.