Cadence Tensilica IP powers Analog Devices’ next-generation DSP architecture - Manila Standard

ADI's pivot from in-house DSP cores to Cadence Tensilica is a candid admission: sustaining an independent processor architecture at advanced nodes has become economically untenable. Tensilica's real edge isn't raw throughput—it's configurability. ADI can now tailor instruction sets and pipeline depth per workload (automotive radar, industrial servo, medical imaging), something fixed-architecture DSPs simply cannot achieve. Upstream, Cadence's IP licensing shifts from a toolchain add-on to architecture-defining power, elevating its pricing leverage toward ARM's Cortex-M tier. Downstream, ADI's customers gain materially better inference efficiency at the edge, directly pressuring Qualcomm's Hexagon in automotive ADAS. The structural risk: ADI now carries generational lock-in to Cadence's Tensilica roadmap. Any shift in licensing terms or IP direction puts ADI's product cadence at the mercy of a third party. Under US export-control frameworks, routing this IP into restricted markets adds non-trivial compliance overhead. Over the next 12–24 months, configurable processors will displace fixed DSPs as the default for edge compute. Expect NXP and Infineon to mirror the IP-licensing playbook by 2026. Qualcomm, in turn, will likely be forced to open Hexagon licensing to defend its automotive install base.