Chinese university builds 3D chip design tool tailored to Huawei's ‘LogicFolding’ architecture — 3D design delivers increased performance and better thermal management - Tom's Hardware

Peking University's School of Integrated Circuits has unveiled a prototype electronic design automation (EDA) tool tailored for Huawei's LogicFolding architecture, a significant step toward domestic c... Read original →

Peking University’s prototype EDA tool for Huawei’s LogicFolding architecture signals a strategic pivot in China’s semiconductor trajectory—bypassing EUV constraints through vertical integration. Technically, it shifts design paradigms from 2D layout assistance to true 3D-aware implementation, directly tackling performance and thermal bottlenecks at mature nodes. From a compliance standpoint, this reduces reliance on U.S.-controlled EDA suites but exposes gaps in sub-7nm verification and IP interoperability. Western rivals like Cadence and Siemens EDA will likely accelerate offshoring sensitive modules to Korea or Vietnam while tightening licensing to Chinese firms. Within 18 months, if domestic players like Empyrean or Primarius commercialize this academic breakthrough, China could establish a viable 'non-EUV high-density' pathway for AI/HPC chips—potentially redefining global 3D IC competition.