Column: 3D memory could redraw chip competition, weaken US sanctions on China

The vertical stacking architecture of 3D NAND carries an inherent "sanction immunity" — core processes center on etching and thin-film deposition, not EUV lithography, making domestic substitution far more tractable than in advanced logic. As the industry scales from 128L toward 232L and 300L, the BIS threshold set in October 2022 has lost its anchoring power. YMTC can continue layering with DUV multi-patterning, while Samsung and SK Hynix face bottlenecks in etch precision and thermal budget, not lithography resolution. The real battleground is etch equipment — Lam Research, Tokyo Electron — and the domestic substitution race involving NAURA and AMEC. NAND's supply chain is structurally shorter than logic's, with fewer chokepoints, which dilutes the actual impact of export controls. For equipment vendors, each additional control tier compounds compliance costs exponentially while narrowing the substitution window for Chinese buyers. The three majors are diverging: Micron has exited, Samsung runs dual-track, SK Hynix bets on V-NAND differentiation. YMTC's layer-count race is fundamentally a capacity-positioning play — once 232L volume production is established, a price gap will open in the enterprise SSD market by 2025-2026. Over the next 18 months, 3D NAND will become the highest "sanction-penetration" category in memory. BIS will likely pivot enforcement toward HBM and advanced packaging, giving China's storage chain a policy vacuum to close the domestic equipment loop above 200L. The "128-layer" line will become a historical footnote.