Following CoWoS, will the next generation of advanced packaging be CoPoS? - 富途牛牛

As the semiconductor industry advances toward more sophisticated process nodes, advanced packaging technologies have become crucial for enhancing chip performance. CoWoS (Chip on Wafer on Substrate), ... Read original →

If CoPoS displaces CoWoS, it will reshape the advanced packaging ecosystem: upstream substrates and interposers demand superior thermo-mechanical stability, while downstream HPC and AI chip designs must adapt to new heterogeneous integration paradigms. For NVIDIA, shifting to CoPoS may alleviate TSMC’s CoWoS capacity constraints but introduces >15% BOM cost hikes due to low yields and equipment incompatibility, amplifying supply chain geopolitical exposure—especially as the U.S. and EU push domestic packaging capacity. Intel and Samsung will accelerate FOVEROS and I-Cube iterations to challenge the TSMC-NVIDIA alliance’s dominance in AI packaging standards. Over the next 18 months, CoPoS won’t see mass adoption but will emerge as a critical fallback for sub-3nm nodes, ultimately forcing OSATs toward IDM-like integration and raising the bar for end-to-end semiconductor competitiveness.