Former Google, Nvidia Execs Launch Company to Ease GPU Crunch - The Information

The GPU crunch is no longer a capacity story—it is an architecture and ecosystem story. When veterans from Google's TPU lineage and Nvidia's data-center division co-found a new vehicle, the signal is unambiguous: the CUDA moat is being flanked, and the true bottleneck has shifted from raw FLOPS to HBM bandwidth, interconnect topology, and software portability. Technical ripple: A chiplet-plus-HBM3E/4 design philosophy will directly strain CoWoS advanced-packaging capacity in China's Taiwan, forcing SK Hynix and Samsung to accelerate HBM roadmaps. EDA tooling and IP licensing (Arm, Synopsys) become the new competitive frontier; advanced packaging upgrades from "supporting role" to strategic asset. Compliance exposure: BIS export controls and the evolving de-minimis threshold add roughly 8–12% to cross-border supply-chain costs. Regulatory fragmentation across the EU Chips Act and Japan's R&D subsidies dilutes single-jurisdiction advantages. Market dynamics: Nvidia's rational play is not a price cut—it is accelerating Blackwell Ultra and deepening NIM/CUDA lock-in. AMD will frame this as validation of its second-source narrative. Hyperscalers will fast-track in-house silicon to reduce single-vendor dependency. Twelve-to-twenty-four-month tail: the bottleneck narrative pivots from "GPU shortage" to "memory and interconnect shortage." The real disruption will not come from a faster GPU—it will come from a software stack that renders heterogeneous compute transparent.