Foundry, test costs push PMIC price hikes toward 12-inch wafers

The PMIC price surge stems from the broken economics of migrating analog-heavy designs to 12-inch fabs. Technically, high-voltage BCD processes resist scaling on advanced logic nodes, causing low yields and soaring test costs—undermining the presumed cost benefits of larger wafers. Regulatory shifts like the U.S. CHIPS Act prioritize digital chips, leaving analog/PMIC investments exposed and supply chains more fragile. In response, IDMs like TI and ADI are tightening pricing control in automotive segments, while TSMC and Samsung lock capacity with strategic clients, marginalizing smaller fabless players. Over the next 12–24 months, expect three ripple effects: specialized high-voltage process development to bypass generic 12-inch constraints; system designers embedding redundant PMICs at the cost of efficiency for supply assurance; and accelerated formation of regional PMIC foundry alliances (U.S.-Japan-EU), fragmenting the global semiconductor ecosystem further.