From GAA to 3D Stacked FET: Expanding the Transistor into the Third Dimension - Samsung Semiconductor

At the 2026 VLSI Symposium, Samsung Electronics' Semiconductor Research Center presented a breakthrough in 3D stacked field-effect transistor (FET) technology, demonstrating the first implementation o... Read original →

Samsung’s triple-stacked nanosheet FET debut at VLSI 2026 signals the definitive shift from 2D scaling to 3D transistor architectures. This leap forces co-optimization across EUV patterning, atomic-layer deposition, and MDI isolation, while demanding a complete overhaul of EDA modeling for vertical devices. Geopolitically, advanced epitaxy tools risk U.S. BIS export restrictions, compelling foundries in Taiwan, China and Hong Kong, China to reassess supply chain exposure. TSMC will likely fast-track its CFET roadmap to defend its process leadership, while Intel may deepen IMEC collaboration to avoid falling behind post-GAA. Within 18 months, pilot production will begin—but thermal dissipation and yield ramp rates will dictate who captures first-mover advantage, turning this into a battle for ecosystem dominance, not just transistor density.