Global suppliers race accelerates: TSMC's first CoPoS demo tools enter validation - digitimes

TSMC is accelerating its CoPoS (Chip on Panel Solution) technology rollout, replacing traditional circular wafers with larger rectangular glass panels to meet packaging demands for AI GPUs and HPC chi... Read original →

TSMC’s push into CoPoS signals a paradigm shift from chip-scale to panel-scale advanced packaging. This move pressures equipment vendors to rapidly adapt EUV and metrology tools for large-format glass substrates, while forcing OSATs to overhaul their circular-wafer-centric production models. Geopolitically, reliance on U.S., Japanese, and Korean glass supply chains heightens export control exposure for Taiwan, China-based fabs, potentially inflating compliance and redundancy costs. In response, Samsung and Intel will likely accelerate Foveros or I-Cube development to counter TSMC’s lead, but yield challenges remain formidable. Within 18 months, if CoPoS scales successfully, it could redefine HPC packaging standards and catalyze co-evolution across EDA, thermal solutions, and server architectures—consolidating TSMC’s dominance through a glass-substrate ecosystem.