GlobalFoundries and TSMC reach $2B deal for US-based silicon interposes - Manufacturing Dive

Silicon interposes are the chokepoint of 2.5D packaging. The GF-TSMC $2B agreement is not a procurement deal—it is a structural decoupling of the most geographically concentrated node in the advanced packaging stack. Technical cascade: Interpose yield governs thermal management and signal integrity in chiplet architectures. Once GF's US 12-inch line reaches volume production, a closed loop forms—US wafer, US interpose, US package—directly undermining Intel's Foveros reliance on external interpose suppliers and squeezing Amkor/ASE pricing power. Compliance exposure: This transaction is almost certainly a precondition for TSMC's Arizona fab to unlock subsequent CHIPS Act tranches. Should export controls tighten further, GF's US facility becomes a safe harbor inaccessible to TSMC's Taiwan, China fabs, with bifurcation costs passing through to end-market AI accelerator pricing. Competitive response: Expect Intel to accelerate in-sourcing of interpose technology (legacy 10nm-era IP) and Samsung to build parallel US packaging capacity ahead of its HBM4 roadmap (2026). The true losers are tier-2 OSATs—once the top two internalize interpose supply, the mid-tier margin pool compresses structurally. 12-24 month outlook: Two to three additional bilateral deals will follow (likely involving Micron's HBM interconnects). "Packaging sovereignty" will drive a 30-40% premium on US-sourced interpose wafers. By 2026, global advanced packaging bifurcates along geopolitical axes, with the US-aligned camp capturing over 60% of AI accelerator volume.