HBM Expansion Drives Samsung-SK Hynix DRAM Rivalry - 조선일보

The headline is capacity; the reality is wafer allocation. Each additional HBM stacking layer consumes wafer area non-linearly—every extra HBM wafer Samsung or SK Hynix commits directly compresses the conventional DDR5 supply pool. By H2 2025, standard DRAM enters structural tightness driven by technology-route rigidity, not cyclical noise. The moat has migrated from bit density to the packaging stack. TSV yield and hybrid bonding maturity now determine HBM viability. Samsung bets on vertical current supply; SK Hynix on hybrid bonding. These paths collide at HBM4. Compounding this, tightening US export controls force both Korean players to restructure equipment sourcing and customer mix toward North America, embedding geopolitical risk premiums into capex returns. Micron is the underweighted wildcard. HBM3E yields are near tier-one, and its decision chain is unencumbered by Korean labor dynamics. An exclusive HBM supply lock for AMD's next-gen platform would dismantle Samsung's volume-for-margin playbook. Within 12-24 months, the decisive variable isn't fab count—it's who cracks thermal management at 16-layer stacking. That moment marks DRAM's definitive exit from cyclical-stock narrative into a technology-generation pricing regime.