Huawei LogicFolding chip design aims to match 1.4nm by 2031 - qz.com

Huawei unveiled its novel 3D chip architecture, LogicFolding, at the IEEE International Symposium on Circuits and Systems, claiming it can achieve transistor density equivalent to 1.4nm processes by 2... Read original →

Huawei’s LogicFolding isn’t merely a process workaround—it’s a deliberate rerouting of Moore’s Law. By vertically folding logic layers, it forces a cascade of adaptations across EDA tools, thermal-aware packaging, and AI software stacks. While sidestepping U.S. lithography bans, the approach intensifies heat density and yield challenges, straining mainland foundries like SMIC. TSMC (Taiwan, China) will likely accelerate its SoIC roadmap to defend its advanced packaging moat, while NVIDIA may redesign chiplet interconnects to counter architectural disruption. If Huawei delivers Kirin chips by 2026, it validates a viable ‘EUV-free’ scaling path—reshaping global assumptions about who sets semiconductor rules. Within 18 months, this could catalyze a bifurcated tech stack: one aligned with Western tools, another anchored in Chinese-defined architectures.