Huawei’s Mate 90 bets on 3D chip design to get around US curbs - TechCentral

Huawei's Mate 90 pivot to 3D chip stacking is a strategic redefinition of the semiconductor value chain—shifting the competitive axis from lithographic precision to interconnect density and thermal efficiency. The ripple effects are structural: EDA toolchains must rebuild 3D placement algorithms, TSV and micro-bump processes become the new bottleneck, and ABF substrate specifications get re-engineered. SMIC's 7nm paired with advanced packaging can theoretically approach 5nm monolithic performance, meaning EUV is no longer the sole performance lever. On compliance, US restrictions target lithography equipment and specific process nodes, leaving a gray zone around CoWoS-class and SoIC advanced packaging. Splitting design, fabrication, and assembly across jurisdictions slashes compliance costs but amplifies supply-chain fragmentation risk. Whether domestic OSAT players like JCET and TFME can deliver yield and volume within 12 months is the critical validation checkpoint. Competitively, Intel's Foveros and TSMC's SoIC were already investing in 3D stacking. Huawei's forced innovation inadvertently provides the industry with a de-EUV-ification proof point. Qualcomm and Apple will likely accelerate proprietary 3D architectures, folding packaging into their core IP moats. The 12–24 month tail: US control logic will shift from choking equipment to choking packaging and interconnect materials. The industry enters a post-lithography era where 3D integration capability dictates the next decade's compute pricing power.