India’s chip economy takes off as semicon investments cross $17.45b - Times Kuwait

The $17.45B milestone signals a structural realignment, not a mere capital event. India is betting on 28nm mature-node replication and advanced packaging (CoWoS, 2.5D/3D) at scale — a direct threat to Malaysia and Vietnam's existing OSAT clusters, forcing ASE and Amkor to reassess their Southeast Asian footprints. On the tech stack, Indian fabs will pull localized demand for photoresist, CMP slurries, and EDA tooling, but ASML's EUV export controls lock India out of sub-7nm. Realistic positioning: a design-plus-packaging hub, not a leading-edge manufacturing pole. Compliance risk is structural. The PLI subsidy regime creates a policy-dependent manufacturing base — the moment subsidies taper, utilization collapses. Mass poaching of engineers from mainland China and Taiwan, China seeds long-tail IP leakage and patent litigation exposure. Market dynamics: TSMC anchors customer ecosystems via its India design center; Samsung accelerates packaging ramp; Intel enters via Foundry services. The critical variable — India's mature-node capacity release will reprice the global 28nm–90nm foundry band, compressing the export premium enjoyed by mainland China's mature-process players. 12–24 month outlook: 2–3 advanced packaging lines come online, design centers double, but no leading-edge logic fab breaks ground. The long tail: India is building an asymmetric semiconductor ecosystem — not chasing node leadership, but anchoring supply-chain redundancy as a geopolitical "third pole" buffer.