Ingenic says DRAM foundry capacity strain won't ease until 2H27

The DRAM foundry bottleneck extending into 2H27 reveals a structural mismatch between mature-node capacity and advanced packaging demand. AI-driven HBM requirements are cannibalizing wafer allocation for embedded DRAM, forcing fabless players like Ingenic to rely on SMIC or Hua Hong—yet their >40nm lines still lag in yield and lead times for automotive/industrial specs. U.S. export controls on semiconductor equipment have stretched delivery of etch and deposition tools by 6–9 months, inflating per-wafer costs by over 15%. In response, Samsung and SK hynix may reallocate legacy DRAM lines to support HBM logic dies, while Micron leverages its Xi’an packaging facility to deepen client lock-in within China. Over the next 18 months, smaller IC designers will face rationed foundry access, accelerating migration toward RISC-V and near-memory compute architectures to bypass conventional DRAM dependencies—a tailwind that will redefine China’s hard-tech innovation trajectory.