Integration still ‘a number of years’ away as GAA address McAleese’s departure - Extra.ie

The simultaneous surfacing of executive turnover and the candid admission that GAA integration remains years from volume production exposes a structural tension the industry has been papering over: FinFET's diminishing returns are colliding with GAA's immaturity in yield and process window. For the next 18-24 months, the big three foundries are locked into a costly dual-track regime—milking 5nm/3nm FinFET for revenue while bleeding capital on 2nm GAA qualification, with capex inflating on both fronts simultaneously. The technical cascade is severe. GAA demands 40+ EUV patterning layers versus roughly 20 for FinFET, making ASML's High-NA delivery cadence the true chokepoint. TCAD simulation complexity explodes exponentially; Synopsys and Cadence's GAA-specific models are still converging. Strategically, TSMC (Taiwan, China) plays the conservative card—waiting for GAA maturity before switching—while Samsung's aggressive 2nm push externalizes yield risk onto early-adopter clients. Intel bets on PowerVia to offset GAA yield penalties, but leadership churn is eroding credibility in its process roadmap. The 12-24 month long tail: GAA won't arrive as a cliff-edge. Advanced packaging (CoWoS, SoIC) will absorb the performance delta that transistor architecture was supposed to deliver, inadvertently extending the Chiplet strategy's window of relevance.