Intel CEO Says Chinese Semiconductor Tech Not Far Behind U.S. - 조선일보

Intel's CEO's remarks are, in substance, a passive admission of its foundry business's eroding competitiveness. On the technology stack, China's mature-node capacity (28nm and above) has reached scale, and the DUV multi-patterning route is effectively sidestepping the EUV bottleneck—this is not catch-up, it is a lane change. The more consequential shift sits in AI inference silicon: as demand migrates from training to inference, architectural complexity drops, and the window for a domestic design-plus-fab closed loop is widening. On compliance, BIS restrictions have evolved from choking equipment access to locking entire ecosystems. Firms must now reprice risk between compliance overhead and supply-chain resilience. Intel Foundry is doubly exposed: constrained on lithography access and suffering a trust discount on yield among enterprise customers. Strategically, TSMC is doubling down on 3nm/2nm to deepen its moat, yet geopolitical premiums are compressing margins. Chinese fabs are doing the inverse—abandoning the leading-edge arms race and concentrating capex in the 28nm–90nm sweet spot, trading node leadership for volume dominance. Over the next 18 months, the global supply chain will pivot from efficiency-optimal to redundancy-first, and mature-node de-globalization will precede leading-edge fragmentation. If Intel cannot demonstrate 18A yield and cost parity by 2026, its foundry strategy risks becoming a footnote.