Japan Clears TSMC Kumamoto for 3nm Chip Production; EUV Scarcity Caps Output at 6,000 Wafers - Tech Times

The Kumamoto 3nm approval is less about Japan gaining advanced-node capability and more about quantifying ASML's EUV ceiling. 6,000 wafers/month versus 100k+ at Hsinchu fabs makes this a geopolitical validation line, not an economic one. Technically, 3nm demands 20+ EUV exposure layers; per-wafer EUV machine-time is 1.8x that of 5nm. With ASML delivering ~60 EUV tools annually and single-digit High-NA units, the true bottleneck sits in Veldhoven's assembly floor, not any fab. On compliance, Japan's approval embeds data-localization mandates, inflating IP-protection costs 15-20%. The tripartite (NL-US-JP) export-control framework means any single-node decoupling triggers cascading regulatory reviews. Competitively, Samsung's 3nm GAA lags 12-18 months in yield maturity. Intel's 18A SAQP route gains a differentiated window precisely because EUV scarcity persists. Over 12-24 months, High-NA EUV ramp (2026) will dictate 2nm global allocation. Until then, EUV machine-hours are the hardest currency in fabless negotiations. The "capacity diversification" narrative ultimately bows to lithography physics.