Japanese Chipmaker Rapidus Plans Cheap 2nm Wafers To Rival TSMC - The Mac Observer

Japanese chipmaker Rapidus plans to launch affordable 2nm wafers to compete with TSMC, marking a significant evolution in the global semiconductor industry landscape. This initiative reflects Japan's ... Read original →

Rapidus’s push for cost-competitive 2nm wafers leverages U.S.-Japan semiconductor alignment to reshape foundry geopolitics. Technically, integrating IBM’s 2nm IP with Japan’s materials and equipment edge could accelerate EUV and high-mobility channel innovations upstream, forcing EDA and advanced packaging co-evolution. Compliance-wise, while likely qualifying for CHIPS Act subsidies, it faces stringent U.S. export controls that inflate hidden operational costs. Against TSMC (Taiwan, China)—which boasts >80% 3nm yield—Rapidus won’t displace premium logic demand soon but may undercut mid-tier AI inference segments, pressuring TSMC to pre-emptively adjust 2nm pricing or capacity allocation. Within 18 months, if Rapidus achieves >30% pilot yield, the industry will pivot from pure node leadership to a dual-track race: performance-per-dollar plus supply chain sovereignty, accelerating de-Taiwanization of non-U.S. semiconductor ecosystems.