JCET Group partners with Wuxi to advance 2.5D advanced packaging facilities - digitimes

JCET's 2.5D packaging bet in Wuxi is not a capacity play—it is a strategic seizure of the AI chip value chain's final mile. The global CoWoS bottleneck sits squarely in TSMC's hands, throttling NVIDIA, AMD, and every major ASIC house. JCET is inserting itself directly into that chokepoint. The binding constraint, however, is not real estate. UV hybrid bonding, precision thinning, and TSV etching tools remain locked behind US, EU, and Japanese export controls. Expect JCET's yield ramp to trail TSMC by 12 to 18 months, with per-unit packaging costs running 15 to 25 percent higher. This is a supply-chain sovereignty problem, not an engineering one. On the competitive front, TSMC will accelerate CoWoS-L and SoIC roadmaps to maintain a two-generation moat at the high end. Samsung's I-Cube and Intel's Foveros leverage front-end-to-back-end vertical integration for bundled advantage. JCET's differentiated window: serving China's domestic AI silicon designers—Ascend, Cambricon, Biren—whose compliance sensitivity outweighs their demand for absolute yield parity. The 12-to-24-month long tail: packaging is graduating from a foundry afterthought to a standalone strategic asset in AI compute. Whoever controls 2.5D capacity controls the throat of the compute supply chain.