Mask Economics Shape High-NA EUV Adoption - Semiconductor Engineering

As semiconductor process nodes continue to shrink, EUV (extreme ultraviolet) lithography is increasingly critical in advanced manufacturing, but its high cost has drawn industry attention. Recent disc... Read original →

Soaring EUV mask costs are forcing a fundamental redesign of chip layout strategies. While High-NA EUV promises single-patterning simplicity at sub-3nm nodes, its stringent CDU and EPE specs strain mask writers from D2S and HJL Lithography, pushing EDA firms like Synopsys to embed ILT deeper into design flows to cut mask layers. Cost-conscious players like Micron delay High-NA adoption, favoring layout-aware cost optimization. Geopolitically, U.S. export controls on advanced litho tools inflate compliance overhead for Chinese fabs, extending High-NA ramp timelines. TSMC (Taiwan, China), backed by NVIDIA’s AI demand, charges ahead with High-NA deployment, while Samsung may counter with hybrid multi-patterning to cap CapEx. Within 18 months, mask economics—not just scaling—will dictate node selection, bifurcating manufacturing into a dual-track model: High-NA for AI/HPC, and mature immersion lithography with self-aligned quadruple patterning for volume mainstream chips.