Peking University's true-3D EDA tool gives Huawei's LogicFolding chip roadmap critical design link

Peking University’s true-3D EDA prototype is far more than an academic milestone—it’s a strategic enabler for Huawei’s LogicFolding architecture. Technically, it bridges critical gaps in thermal-electrical co-simulation and 3D-aware physical design, reducing reliance on legacy planar EDA flows and pressuring domestic players like SMIC and JCET to fast-track 3D integration capabilities. From a compliance standpoint, it circumvents U.S. export controls on Synopsys’ and Cadence’s advanced 3D tools, slashing Huawei’s design risk below the 14nm node. Competitively, TSMC may accelerate SoIC access for Taiwan, China clients, while Samsung could push its X-Cube stack into mainland China. Within 12–24 months, if productized, this tool could catalyze a self-reliant Chinese ecosystem for HBM-plus-logic 3D integration—potentially reshaping global discourse around post-Moore scaling beyond Intel’s or NVIDIA’s roadmaps.