Qualcomm's proposed solution to catch up in AI infra: Bury the compute under the DRAM - The Register

Qualcomm unveiled a new approach to AI infrastructure at its 2026 investor day, aiming to overcome the memory wall in AI inference by embedding compute units under DRAM in a high-bandwidth compute (HB... Read original →

Qualcomm’s HBC architecture is a strategic detour around the CoWoS packaging bottleneck. By embedding compute under LPDDR5x stacks, it sacrifices raw bandwidth versus HBM3e but sidesteps reliance on TSMC’s Taiwan-based CoWoS capacity—mitigating supply chain fragility. This move will accelerate SRAM and TSV co-integration in near-memory computing and force MLIR compilers to adapt to heterogeneous memory topologies. However, its claimed 133 TB/s 'effective bandwidth' lacks standardized validation, inviting skepticism. Against Nvidia’s Grace Hopper and AMD’s MI300X full-stack dominance, Qualcomm must leverage Modular’s Mojo language to build software differentiation. Over the next 18 months, success hinges on securing cloud vendor design-ins for inference workloads and tapping U.S. CHIPS Act subsidies for domestic advanced packaging—otherwise, it remains confined to the mobile periphery, unable to breach the AI datacenter core.