Rethinking Chip Verification - Semiconductor Engineering

As semiconductor process nodes continue to shrink, the complexity of chip design and verification is increasing exponentially, making traditional verification methods inadequate. Recently, the industr... Read original →

The verification bottleneck has evolved from a technical hurdle into a systemic engineering crisis. At sub-3nm nodes and with 3D packaging, legacy UVM and RTL flows collapse under the weight of geometric, thermal, and material semantics. The so-called 'golden specification' is in fact an AI-driven cross-domain contract—demanding that IP-XACT and SystemRDL evolve into executable, inferable semantic ontologies, not static documents. This forces EDA vendors like Synopsys and Siemens EDA to embed DRC and system simulation within MBSE frameworks, while startups like Axiomise bet on AI-native spec engines. For foundries in Taiwan, China and globally, lacking AI-friendly spec infrastructure risks rendering advanced-node capacity unverifiable. Over the next 18 months, the industry will battle over ‘spec-as-code’ standards, with Arteris and Vinci leveraging IP integration to dominate system-level verification entry points. Export controls are also expanding to cover verification IP and AI models themselves, compelling firms to embed auditable, traceable spec lineage from day one.