Industry Analysis
Chey Tae-won's insistence on accelerating the Honam cluster despite slippage is a geopolitical positioning move, not a routine capex cycle. The US CHIPS Act and EU Chips Act have crystallized a friend-shoring architecture; SK Hynix, locked into NVIDIA's HBM3E supply chain, is being pulled into its core. The Honam siting—deliberately outside the Seoul metro's power and talent constraints—signals a calculation: AI-driven HBM consumption will outpace the cluster's ramp curve, and each quarter of delay burns hundreds of millions in lost shipment windows.
The real moat isn't the DRAM die. It's advanced packaging (2.5D/3D stacking) and materials vertical integration. The delay almost certainly traces to Jeonnam grid expansion, ASML/AMAT lead times, and a packaging-talent vacuum. Forcing acceleration inflates compliance overhead—simultaneously serving US AI customers and mainland China OEMs under export-control regimes adds an estimated 15-20% to opex.
Competitively, TSMC (Taiwan, China) SoIC and Samsung X-Cube are racing to capture the packaging value layer. SK's defensibility rests on HBM yield and customer lock-in, not logic nodes. Over the next 12-24 months, the HBM4 transition (2025-2026) is the inflection: packaging capacity, not memory wafers, becomes the binding constraint. If Honam ramps on schedule, SK captures packaging margins; if it slips again, TSMC and Samsung intercept the value.
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