SoftBank, Intel target HBM limits with 9-layer memory

SoftBank’s SAIMEMORY and Intel targeting 9-layer 3D DRAM isn’t just an engineering feat—it’s a strategic bypass of AI hardware’s thermal ceiling. This move pressures TSV and hybrid bonding ecosystems, threatening Micron and SK Hynix’s HBM3E lead. Upstream, AMAT and Tokyo Electron will see surging demand for sub-micron packaging tools; downstream, GPU makers risk 'compute idling' without co-optimized memory subsystems. Geopolitically, the alliance skirts current U.S. advanced packaging controls—but if BIS classifies 9-layer DRAM as restricted, supply chain costs could spike over 15%. Samsung will likely counter with HBM4 plus optical I/O, while TSMC’s CoWoS capacity becomes the next battleground. Within 18 months, HBM transitions from a bandwidth metric to a thermal design cornerstone, accelerating near-memory compute architectures.