Swapping Out Chiplets: I/Os Vs. Compute - Semiconductor Engineering

As the semiconductor industry advances toward more advanced process nodes, chiplet architectures are becoming a dominant design trend. This approach allows architects to swap out specific chiplets whi... Read original →

Chiplet architectures are shifting from optional to strategic imperatives. At 3nm and below, compute chiplets iterate rapidly with process nodes, while I/O chiplets—constrained by slower protocol evolution (e.g., PCIe 6.0 to 7.0)—become reuse anchors, forcing EDA vendors like Cadence and Synopsys to enhance multi-die signal integrity and thermal co-simulation. Geopolitically, TSMC’s (Taiwan, China) CoWoS capacity has become the AI chip arms race bottleneck, compelling NVIDIA to pre-book 2027 packaging slots and hardening supply chains. U.S. export controls on advanced packaging tools may delay non-U.S. players’ I/O upgrades, inflating validation costs. Over the next 18 months, UCIe 2.0 and CXL ecosystems will enable plug-and-play chiplet markets—but only firms owning SerDes and LPDDR6 PHY IP will command pricing power. Interconnect IP providers like Arteris risk marginalization if they fail to integrate tightly with foundry PDKs.