The quest for better chip design accelerates - Fierce Sensors

As AI and IoT technologies advance, chip design is facing unprecedented complexity. Synopsys has launched 'Multiphysics Fusion', integrating Ansys' multiphysics simulation into its EDA tools to improv... Read original →

Synopsys’ integration of Ansys’ multiphysics simulation signals a paradigm shift in EDA—from isolated tools to system-aware co-design. Technically, embedding thermal, power, and mechanical stress analysis at RTL stage mitigates IR drop and hotspots that cripple 2nm yields, saving up to 35% die area—equivalent to nearly 10 extra H100-class chips per wafer. Regulatory pressures are mounting as the U.S. and EU tighten EDA export controls on advanced nodes, pushing Samsung and MediaTek to validate domestic alternatives, though escaping the Synopsys-Cadence duopoly remains impractical short-term. Cadence counters with its Future Facilities acquisition for system-level simulation, while Siemens pushes Xcelerator for IC-package-board convergence. NVIDIA’s deep integration with Synopsys via Grace Hopper effectively locks in an AI design moat. Within 18 months, AI-driven autonomous design flows will emerge—but geopolitical fragmentation risks bifurcating global design standards, inflating R&D costs for multinationals.