Touch Taiwan 2027 expands tech scope with advanced packaging and SiPh shows

The convergence of advanced packaging and silicon photonics into a single exhibition track is the most telling signal here. CoWoS capacity has become the binding constraint on AI accelerator delivery, and copper interconnects are hitting physical walls beyond 1.6T. The industry is effectively rewriting the post-Moore roadmap with "packaging as the new process node." Upstream, demand for glass substrates, ABF laminates, and underfill materials will inflect sharply. Downstream, HPC interconnect architectures will shift from chip-cable-chip to co-packaged optics. EDA toolchains that cannot co-design 3D stacks with photonic devices will see design cycles erode yield gains. On supply-chain risk, advanced packaging capacity remains heavily concentrated in Taiwan, China, while silicon photonics IP is scattered across the US, Europe, and Japan. This geographic fragmentation is a systemic vulnerability under escalating geopolitical friction. Firms relying on a single packaging node for their entire output carry operational fragility that the 2022 chip shortage should have made painfully clear. Competitively, Samsung and Intel will almost certainly fold silicon photonics into their packaging roadmaps before 2027 to blunt TSMC's CoWoS head start. Broadcom and Marvell are likely to accelerate M&A in optical-engine startups to lock in CPO IP leverage. Within 18 months, expect two to three packaging-photonics deals to close, glass substrates to enter volume production, and "advanced packaging + SiPh" to migrate from exhibition buzzword to a standard line item on the BOM.