TSMC expands CoWoS and SoIC capacity on AI boom - digitimes

TSMC announced on May 14, 2026, that it is rapidly expanding its CoWoS (chip-on-wafer-on-substrate) and SoIC (system-on-chip) advanced packaging capacity, driven by surging AI demand. The company is c... Read original →

TSMC’s aggressive CoWoS and SoIC capacity build-out is a structural bet on the AI compute arms race. Technically, it forces HBM, silicon photonics, and chiplet ecosystems to accelerate upgrades, dragging EDA and test equipment into urgent co-evolution. Compliance-wise, spreading 18 new fabs across the U.S., Japan, and Europe diversifies geopolitical exposure but inflates capex and localization costs—especially as U.S. CHIPS Act subsidies taper. Competitively, Samsung and Intel may undercut on mid-tier packaging deals, yet lack TSMC’s 3nm-plus SoIC design integration edge. Over the next 12–24 months, advanced packaging capacity—not wafer output—will become the tighter bottleneck. Firms mastering heterogeneous integration will dictate AI chip pricing, while customers over-reliant on single-source supply face mounting delivery and negotiation risks.