TSMC says panel packaging won't replace CoWoS anytime soon for the largest future AI processors — wafer-level tech can scale to 58 massive dies in one package

At TSMC's recent European Technology Symposium, senior vice president Kevin Zhang emphasized that while panel-level packaging technologies offer potential for larger chip packages, they will not repla... Read original →

TSMC’s stance that panel-level packaging won’t displace CoWoS soon reveals a critical truth: scaling package area doesn’t equate to scalable system integration. Upstream suppliers of EUV and interposers will keep prioritizing high-density interconnects for 3nm/2nm nodes, while NVIDIA’s post-Blackwell GPUs remain locked into CoWoS’s 58-die ceiling. Geopolitically, U.S.-led domestic advanced packaging initiatives betting on panel tech risk inflated AI chip costs due to immature tooling and yield issues, undermining supply chain credibility. Samsung and Intel are likely to double down on wafer-based 3D stacking like Foveros or I-Cube to sidestep panel-level uncertainties. Over the next 18 months, CoWoS capacity will become the ultimate bottleneck—and bargaining chip—while panel solutions remain confined to niche, low-power edge AI applications until process maturity arrives post-2030.