UK Semiconductor Catapult launched - Electronics Weekly

The UK's semiconductor Catapult is not an innovation accelerator—it is London's post-Brexit play to re-anchor itself in the design-to-manufacturing value chain. Technical ripple: Britain's moat has never been wafers. It is ARM architecture, EDA toolchains, and advanced packaging IP. The Catapult will almost certainly accelerate chiplet interconnect standards, 3D stacking, and RISC-V ecosystem localization. Upstream, EDA vendors' UK R&D centers gain policy premium; downstream, automotive and medical chip designers see materially lower IP acquisition costs. Compliance exposure: Post-Brexit, the UK has exited the EU's unified export-control regime. The Catapult signals London is building a dual-track framework—US-aligned plus independent certification. For UK IP licensing networks operating in mainland China, technology-transfer review granularity will tighten, pushing compliance costs up an estimated 15–25%. Market dynamics: The US CHIPS Act, EU Chips Act, and Japan's subsidy wave have already absorbed most manufacturing-side capital. With no fabs, the UK's differentiation must hinge on design, packaging, and standards. TSMC will likely treat the Catapult as an IP procurement channel, but ASML should watch for UK influence in advanced-packaging equipment standards. 12–24-month outlook: Expect joint R&D agreements with at least two European fabs, focused on 2.5D/3D packaging and SiC/GaN devices. The real long-tail effect is not capacity—it is whether the UK secures a rule-making seat in RISC-V and open-standard ecosystems. That is the card London actually wants.