Semiconductor News & Analysis Feed
307 articles
2026-06-17
www.ad-hoc-news.de
2026-06-17
AD HOC NEWS
Synopsys Inc., US8716071076
Synopsys AI Product Suite ushers in a new era of chip design automation
17.06.2026 - 00:25:28 | ad-hoc-news.de
Synopsys AI Product Suite targets chip makers racing to tape out faster with fewer engineers and rising complexity.
Synopsys Inc., US8716071076
Synopsys AI Product Suite ushers in a new era of chip design automation
By Alex Weber, ad-hoc-news, June 16, 2026
2026-06-16
www.bisinfotech.com
2026-06-16
Bisinfotech
www.bisinfotech.com
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2026-06-16
news.engineering.asu.edu
2026-06-16
Arizona State University (ASU)
news.engineering.asu.edu
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2026-06-15
evertiq.com
2026-06-15
Evertiq
© geralt/Pixabay
General | June 15, 2026
Cadence unveils fully autonomous virtual engineer for chip design
Evertiq
Built on Cadence’s AI-driven electronic design automation (EDA) portfolio with Nvidia Nemotron models, and secured by Nvidia OpenShell runtime, the new agentic capabilities enable customers to run dynamic simulations in automated workflows.
US company Cadence has announced the indust
2026-06-12
www.scmp.com
2026-06-12
South China Morning Post
Semiconductors
TechBig Tech
China’s chip design software firms back Huawei’s new scaling law. But can they catch US rivals?
Domestic chip design software vendors embrace Huawei’s Tau Scaling Law, but analysts caution that breaking US dominance is far from easy
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Ann Caoin Shanghai
Published: 6:54pm, 12 Jun 2026Updated: 7:00pm, 12 Jun 2026
China’s
2026-06-12
www.scmp.com
2026-06-12
South China Morning Post
Semiconductors
TechBig Tech
China’s chip design software firms back Huawei’s new scaling law. But can they catch US rivals?
Domestic chip design software vendors embrace Huawei’s Tau Scaling Law, but analysts caution that breaking US dominance is far from easy
3-MIN READ
8
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Ann Caoin Shanghai
Published: 6:54pm, 12 Jun 2026Updated: 7:00pm, 12 Jun 2026
China’s c
2026-06-12
www.digitimes.com
2026-06-12
digitimes
Cadence and Intel Foundry are expanding their collaboration on advanced chip design, a move that could affect future semiconductors used in devices and data centers worldwide. The agreement aims to improve performance, power efficiency, and design readiness...
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2026-06-12
digitimes.com
2026-06-12
Cadence and Intel Foundry are expanding their collaboration on advanced chip design, a move that could affect future semiconductors used in devices and data centers worldwide. The agreement aims to improve performance, power efficiency, and design readiness as chipmakers race to bring next-generation technologies to market.
2026-06-12
eetimes.com
2026-06-12
Rebellions leverages memory-centric AI chip designs with SK Hynix and Samsung to fuel IPO ambitions.
2026-06-11
semiengineering.com
2026-06-11
Semiconductor Engineering
Energy-efficient SoC design, optimizing PPA, deep low-voltage operation, and advanced power management techniques.
Access “Foundation IP: Pushing the Boundaries of Energy-Efficient Chip Design” to explore six articles that explain how to address SoC design challenges using advanced Foundation IP solutions. Learn how these approaches enable energy efficiency, high performance, and reliability acro
2026-06-11
www.miragenews.com
2026-06-11
Mirage News
Science
11 JUN 2026 5:18 PM AEST
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Europe Boosts Chip Design, DTU Unites Researchers
Technical University of Denmark
Chip design has attracted growing attention in Europe in recent years. This momentum was clearly visible last week, when DTU hosted a two-day summer school on chip design for PhD students, followed by the international conference Async 2026 (The International Symposium on Async
2026-06-11
www.megabites.com.ph
2026-06-11
megabites.com.ph
At Computex 2026, Cadence (Nasdaq: CDNS) announced the industry’s first fully autonomous virtual agentic AI design engineer, extending the ChipStack™ AI Super Agent to Level-5 autonomy. Built on Cadence’s AI-driven electronic design automation (EDA) portfolio with NVIDIA Nemotron models, and secured by NVIDIA OpenShell runtime, the new agentic capabilities enable customers to run dynamic simulatio
2026-06-11
www.indexbox.io
2026-06-11
IndexBox
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2026-06-11
eetimes.com
2026-06-11
“We are definitely not an EDA company,” Ricursive co-founders told EE Times.
2026-06-11
news.google.com
2026-06-11
EE Times
2026-06-10
technode.global
2026-06-10
TNGlobal
Malaysia-based fabless custom chip design company GreatAsic has raised $6.9 million in a Pre-Series A round led by Vertex Ventures Southeast Asia & India, with participation from Ehsan Kapital and Gobi Partners.
In a statement on Tuesday, Vertex Ventures said the investment is in line with Malaysia developing front-end chip design capabilities beyond its traditional role in semiconductor assembly
2026-06-10
news.google.com
2026-06-10
EE Times
2026-06-09
www.citybiz.co
2026-06-09
citybiz
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GLOBAL, SAN FRANCISCO AI, GENERAL BUSINESS, MERGERS & ACQUISITIONS
Celera Semiconductor Acquires SiliconGate to Expand AI-Driven Analog Chip Design Capabilities
JUNE 9, 2026
Celera Semiconductor has acquired Portugal-based SiliconGate, a specialist in analog integrated circuit design and supply, in a move aimed at expanding its engineering capacity and accelerating
2026-06-09
manufacturing.economictimes.indiatimes.com
2026-06-09
ET Manufacturing
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2026-06-09
digitimes.com
2026-06-09
Huawei's chip design arm HiSilicon Technologies has reportedly raised prices for some products, drawing market attention as China's semiconductor sector shows signs of recovery after a prolonged downturn.