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Cadence has recently worked out a new deal with Samsung Foundry that pushes their existing partnership to a new high, as they focus on 2nm chip design for AI-heavy workloads, starting from concept to deliverable products, especially as designs get more complex with AI, HPC, and 3D-IC integration. For Cadence, they are expanding their Memory and Interface IP portfolio on Samsung’s second-generatio

The agreement adds memory and interface IP, including SerDes, PCIe, UCIe and NVLink-C2C support for AI and HPC designs. Cadence and Samsung Foundry have announced development of a portfolio of memory and interface IP and expanded certification of Cadence digital, custom, 3D IC and system design and analysis flows for Samsung Foundry’s second-generation 2nm process. The work is intended to support

This year’s EE Times Chiplets event will address challenges in the design flow and chiplet technologies to enable straightforward scaling.