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OpenAI’s 700W Jalapeño ASIC outpaces 1,400W Nvidia flagship GPU — claims up to 1.9x throughput per kilowatt and 3.6x lower latency, co-developed with Broadcom - Tom's Hardware

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www.tomshardware.com 2026-08-26

LG enters chip packaging arena with Laser Direct Imaging machine, as TSMC's CoWoS remains constrained — maskless machine is designed to pattern fine interconnects, trading resolution for higher throughput - Tom's Hardware

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www.tomshardware.com 2026-08-21

Exploring Apple Silicon’s local AI performance with the Mac Studio and M4 Max — M4 Max beats GB10 and Strix Halo in decode throughput, but memory bandwidth isn't everything

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tomshardware.com 2026-07-30

This article provides an in-depth analysis of Apple's M4 Max chip's performance in local AI computing, particularly when compared to NVIDIA's GB10 and AMD's Strix Halo platforms. The tests reveal that the M4 Max outperforms these systems in decoding throughput, especially in large language model (LL

Apple Silicon Local AI M4 Max NVIDIA GB10 AMD Strix Halo Memory Bandwidth GPU Performance Mac Studio

AMD launches 2nm Epyc Venice, touts 2.2x throughput over Nvidia Vera - CHOSUNBIZ - Chosunbiz

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biz.chosun.com 2026-07-24

AMD EPYC Venice CPUs Stomp NVIDIA’s Vera With 20% Faster Single-Core & 2.2x Higher Throughput With Up to 256 “Zen 6” Cores, 203 Billion Transistors & Over 5 GHz+ Clocks - Wccftech

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wccftech.com 2026-07-24

AMD has officially launched its EPYC Venice CPU family, featuring the new Zen 6 architecture and built on TSMC's 2nm process technology. These chips are the industry's first 2nm HPC CPUs, offering up to 256 cores, 512 threads, and peak frequencies exceeding 5GHz. Benchmarks show a 20% improvement in

AMD EPYC Zen 6 CPU Performance 2nm Process Agentic AI NVIDIA Vera

AMD and Cerebras partner on low-latency, high-throughput AI inference

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tomshardware.com 2026-07-24

AMD and Cerebras have partnered to develop a low-latency, high-throughput AI inference platform, combining AMD's EPYC processors in Helios rack-scale infrastructure with Cerebras' Wafer-Scale Engine (WSE) solutions. The platform aims to optimize different stages of inference workloads by assigning t

AI Inference Semiconductor Partnership CPU-GPU Collaboration Data Center Architecture AI Chips Low Latency Computing High Throughput Processing Heterogeneous Computing

ASML looks to increase prices of its Low-NA EUV tools beyond existing productivity-based model — company wants to capture the value of all the advantages its tools offer, not just wafer throughput improvements

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tomshardware.com 2026-07-17

ASML is considering shifting its pricing model for low-numerical-aperture (Low-NA) EUV lithography tools beyond the current productivity-based approach, aiming to capture the full value of all technological advantages these systems offer. While the company has long used value-based pricing tied to t

Semiconductor Equipment EUV Lithography ASML TSMC Photolithography Chip Manufacturing Value-Based Pricing Supply Constraints

ASML looks to increase prices of its Low-NA EUV tools beyond existing productivity-based model — company wants to capture the value of all the advantages its tools offer, not just wafer throughput improvements - Tom's Hardware

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www.tomshardware.com 2026-07-17

NVIDIA Vera CPU Boosts AI Factory Throughput to Accelerate Agentic Workloads | NVIDIA Technical Blog - NVIDIA Developer

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developer.nvidia.com 2026-07-07

NVIDIA's new Vera CPU enhances AI factory throughput by optimizing CPU performance for agentic workloads. Agentic systems rely on multi-step workflows combining inference, tool use, code execution, and retrieval, where the CPU plays a critical role in coordinating GPU resources and managing intermed

AI Factory Agentic Systems CPU Performance GPU Acceleration Reinforcement Learning NVIDIA Vera AI Inference KV Cache

TSE Develops Next-Generation HBM Test Handler That Doubles Inspection Throughput - thelec.net

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www.thelec.net 2026-06-19

South Korean semiconductor test equipment maker TSE is developing a next-generation test handler aimed at significantly boosting inspection throughput for high-bandwidth memory (HBM) devices. Developed in collaboration with the Korea Institute of Industrial Technology (KITECH), the system is expecte

Semiconductor Test Equipment High-Bandwidth Memory HBM Test Handler Wafer Testing Semiconductor Manufacturing Test Handler Technology Automated Test Equipment Die-Level Testing

Tensordyne’s 3nm Napier AI Chip Promises 13x Higher Token Throughput Than Blackwell & Blazes Past Rubin With 1000 Tokens/s In Multi-Trillion Parameter Models - Wccftech

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wccftech.com 2026-06-16

Tensordyne, a US-based AI company, has announced the successful tape-out of its Napier AI chip, which claims to outperform NVIDIA's Blackwell and Rubin chips in token throughput and energy efficiency. Built on TSMC's 3nm process, the Napier chip leverages novel logarithmic AI math, tightly integrate

AI chip Semiconductor 3nm process NVIDIA Tensordyne AI inference Chip performance Compute throughput

Boosting MoE Training Throughput with Advanced Fusion Kernels | NVIDIA Technical Blog - NVIDIA Developer

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developer.nvidia.com 2026-06-16

NVIDIA's technical blog explores how advanced fusion kernels significantly boost the training throughput of Mixture-of-Experts (MoE) models. As MoE becomes a foundational component of large-scale AI systems, optimizing these blocks is critical for maximizing training efficiency. NVIDIA introduces cu

Mixture-of-Experts AI Training Optimization GPU Performance Deep Learning Acceleration NVIDIA Technical Blog cuDNN Frontend Transformer Engine Megatron-Core

Run DiffusionGemma on NVIDIA for Developer-Ready, High-Throughput Text Generation | NVIDIA Technical Blog - NVIDIA Developer

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developer.nvidia.com 2026-06-11

NVIDIA's technical blog highlights the deployment of DiffusionGemma, a text generation model developed by Google DeepMind, optimized for NVIDIA platforms. This model introduces a novel approach using diffusion-based denoising to generate 256 tokens in parallel per step, achieving up to 1,000 tokens/

AI text generation NVIDIA GPU DiffusionGemma parallel computing large language model low-latency inference multimodal AI enterprise AI applications

Amazon unveils 'Resilient Network Graphs' data center network that cuts hardware by 69% and boosts throughput by 33%

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tomshardware.com 2026-05-29

Amazon has unveiled its new 'Resilient Network Graphs' (RNG) data center networking architecture, which claims up to 33% higher throughput while reducing power consumption by 40%. This innovation, based on random graph theory, replaces traditional hierarchical 'fat-tree' topologies with a flatter, m

Data Center Networking Network Architecture AWS Random Graph Theory Throughput Improvement Hardware Cost Reduction Energy Efficiency Network Device Optimization

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