Semiconductor News & Analysis Feed

AI-driven hyperscale data center expansion is pushing the global AI race beyond raw GPU computing power into a broader contest over high-speed interconnects and electro-optical integration. As Nvidia's next-generation AI factory moves toward petabyte (PB)-scale data transfers, co-packaged optics (CPO) is heading toward commercialization, lifting the importance of key components such as fiber array

Co-packaged optics (CPO) is rapidly emerging as a foundational architecture for next-generation AI infrastructure. With Nvidia's latest Scale-Up CPO switch roadmap now taking shape, bandwidth per AI rack is set to increase from approximately 130 TB/s in the Blackwell generation to more than 1 PB/s in the Feynman era, spanning Blackwell, Rubin, Rubin Ultra, and Feynman platforms. As a result, the g

China's LineShine supercomputer debuted at No. 1 on the June 2026 TOP500 list, announced at the ISC 2026 conference in Hamburg, becoming the first system to sustain more than two exaflops on the standard HPL benchmark using CPUs only. The result marks the first time since 2017 that a China-based system has led the TOP500 ranking, and reflects Beijing's effort to present a frontier computing system

United Nova Technology (UNT) is expanding from automotive and industrial chips into AI server power management and optical interconnects through a CNY20 billion (US$3 billion) 12-inch mixed-signal fab project.

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Chinese CMOS image sensor supplier SmartSens Technology announced on May 26 that it has entered into a strategic partnership with Chinese IC design company Unisoc to jointly develop Micro LED-based high-speed optical interconnect technology, targeting applications in AI computing clusters, smart vehicles, and industrial vision.

Marvell Technology has said its custom silicon business and data center solutions are emerging as central pillars of its long-term growth strategy, driven by rising demand from hyperscale cloud customers building AI infrastructure, including XPUs, Ethernet switching systems, and high-speed optical interconnects.

Huawei's Tau Law proposal is rapidly redirecting attention across China's semiconductor industry away from pure lithography competition and toward advanced packaging, 3D stacking, optical interconnects, and system-level architecture design.

SmartSens and Unisoc have formed a strategic partnership to develop Micro LED high-speed optical interconnects, aiming to deliver domestic, low-power, high-bandwidth solutions for short-reach AI cluster links. The collaboration could accelerate the commercialization of Micro LED co-packaged optics (CPO) technology and strengthen China's role in global AI infrastructure supply chains, according to

Huawei's Tau Law proposal is rapidly redirecting attention across China's semiconductor industry away from pure lithography competition and toward advanced packaging, 3D stacking, optical interconnects, and system-level architecture design. Some subscribers prefer to save their log-in information so they do not have to enter their User ID and Password each time they visit the site.

Ennostar Holdings' transformation has begun to show clear results, with chairman Paul Peng saying the company's "3+1" strategy is taking shape, as higher-value applications now account for more than half of revenue. Despite continued uncertainty in the global environment, Peng remains cautiously optimistic about the second half of 2026 and expects the company to maintain relatively strong performa

As artificial intelligence workloads continue to expand, demand for memory capacity and bandwidth is growing rapidly, pushing existing GPU-HBM architectures toward their limits. According to ZDNet, researchers at a major South Korean memory manufacturer stated that memory and packaging companies are exploring a new approach that places the GPU and HBM in separate packages. Unlike traditional desig

As AI pushes semiconductors toward new limits in energy, memory, and interconnects, imec’s CEO says future progress will depend on deep co-optimization across the entire computing stack.