AMD CTO Mark Papermaster on 'Zen', 2nm chiplets and the future of supercomputing - Scientific Computing World

Papermaster's anchoring of 2nm chiplets to supercomputing is a structural rejection of Intel's monolithic-die philosophy, not a mere process upgrade. The technical ripple extends beyond the die: SoIC and CoWoS packaging capacity becomes the new binding constraint, HBM4 bandwidth demands force memory vendors into accelerated 3D stacking, and UCIe interconnect maturity will determine whether multi-chiplet systems deliver real efficiency gains. On risk, AMD's singular dependence on TSMC's N2 node creates systemic vulnerability under tightening export controls. If geopolitical friction escalates, the geographic concentration of 2nm capacity is a more lethal chokepoint than EUV lithography itself. Competitively, Intel's 18A backside power delivery, if it ships on schedule, will force AMD to lock in 2nm yield premiums during the Zen 6 window. NVIDIA's Grace-Blackwell vertical integration continues to compress AMD's pricing power in HPC. The 12-24 month tail: chiplet economics will shift from a performance race to a packaging-capacity race. AMD's real moat is not transistor density but ecosystem influence over chiplet interoperability standards.