ASML, TSMC and Imec scale 2D transistors to 50nm pitch on 300mm wafers - Bits&Chips

ASML, TSMC, and imec have achieved scalable 2D transistor manufacturing on 300mm wafers with a 50nm pitch, marking a significant step toward industrial adoption of post-silicon logic devices. Presente... Read original →

The successful integration of 2D transistors at 50nm pitch on 300mm wafers by ASML, TSMC (Taiwan, China), and imec isn’t a lab curiosity—it’s a strategic pivot to extend Moore’s Law. Technically, combining EUV lithography with a reverse thin-film architecture forces upstream material suppliers to industrialize high-purity transition metal dichalcogenides (e.g., MoS₂) and compels EDA vendors to overhaul quantum-aware device modeling. From a compliance standpoint, if this path targets sub-7nm logic, it may trigger new U.S. export controls on 2D-material processing tools, inflating supply chain costs. Competitively, Samsung and Intel will likely fast-track their own pilot lines while doubling down on chiplet-based heterogeneous integration to sidestep single-device scaling limits. Within 18 months, the industry faces a ‘quasi-industrial’ validation window: sustained >90% yield could ignite the first risk-production line by 2027, marking the true dawn of post-silicon logic.