Cadence Expands DTCO Partnership With Intel Foundry Starting From 14A Process - thelec.net

Cadence Design Systems has announced a multi-year collaboration with Intel Foundry to advance Design Technology Co-Optimization (DTCO) for next-generation semiconductor manufacturing, beginning with I... Read original →

Intel Foundry’s deepened DTCO collaboration with Cadence on the 14A node signals a strategic pivot toward becoming a credible third-party foundry. Technically, this accelerates PDK standardization and tightens EDA-process co-design, giving Cadence an edge in serving AI-focused fabless firms. From a compliance standpoint, U.S. export controls on advanced nodes compel Intel to diversify EDA dependencies—relying solely on Synopsys would heighten supply chain fragility. Competitively, TSMC and Samsung may counter by bolstering ties with regional EDA players like S2C in Taiwan, China, to fortify their ecosystems. Synopsys, already embedded in 18A, now faces deliberate vendor-balancing by Intel. Over the next 12–24 months, DTCO maturity will dictate foundry competitiveness; PDK readiness and toolchain reliability will directly sway tape-out decisions and reshape chiplet integration standards globally.