Industry Analysis
JCET's $1.1B advanced packaging plant in Shanghai isn't just capacity scaling—it's a strategic bet on 'packaging as fabrication' as AI chips hit physical limits. With sub-3nm nodes constrained by EUV export controls, Chiplet and 2.5D/3D integration become the only viable performance levers, directly boosting demand for domestic high-density substrates, thermal solutions, and test equipment. Geopolitically, reliance on U.S., Japanese, or Korean tools still exposes JCET to licensing risks, but deep integration with Chinese AI chipmakers like Huawei Ascend creates a de facto 'de-Americanized' supply chain. TSMC (Taiwan, China), though dominant in CoWoS, prioritizes NVIDIA, leaving room for JCET to lock in domestic LLM firms. Within 18 months, China’s packaging capacity surge will force OSAT rivals like ASE and Amkor into defensive tech-sharing deals, while packaging’s value share in advanced chips could double from 10% to 20%, making it the new frontline of semiconductor localization.
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