HBM supply constraints to keep memory prices rising through 2027 - TrendForce - Telecompaper

HBM capacity cannibalization has evolved from a cyclical swing into a structural repricing of the memory industry, driven by the AI compute arms race. Technically, HBM4's 16-layer TSV stacking consumes 3-4x the DRAM wafer area of DDR5. The big three have redirected over 70% of advanced DRAM capacity to HBM, effectively draining the DDR5/LPDDR5 supply pool. Upstream, hybrid-bonding equipment (BESI, ASMPT) has become the new bottleneck; downstream, memory now accounts for over 25% of AI accelerator BOM cost, shifting pricing power irreversibly toward memory makers. On compliance and risk: US export controls on advanced packaging equipment continue to tighten, and Taiwan, China's CoWoS capacity represents a single-point-of-failure for global AI chip delivery. In a three-oligopoly structure, any yield disruption triggers price shocks—Samsung's repeated HBM3E qualification failures are a cautionary precedent. Strategic positioning: SK Hynix has locked in exclusive HBM4 supply for NVIDIA through 2026; Micron is penetrating AMD's chain via HBM3E; Samsung is forced into a price-volume trade. CXMT's HBM2E progress won't disrupt the oligopoly before 2027 but will become a price-anchor variable thereafter. Outlook: Over the next 18 months, "memory inflation" will replace "chip shortage" as the dominant cost narrative in AI. HBM4 mass production won't ease conventional DRAM tightness—hybrid bonding yield ramp requires 12+ months, while inference-side HBM demand growth will outpace training. The DRAM price-down channel is effectively closed through 2027. Memory makers' pricing power has undergone a structural transfer.