Huawei claims sanctions-busting breakthrough with 1.4nm-class chips by 2031, claims 55% higher transistor density — firm claims new LogicFolding chip architecture can bypass EUV restrictions, introduces 'Tau Scaling Law' to replace Moore's Law - Tom's Hardware

Huawei has unveiled a breakthrough chip design technology aimed at overcoming U.S. sanctions, targeting 1.4nm-class chips by 2031. The innovation is based on a novel 'LogicFolding' architecture and a ... Read original →

Huawei’s LogicFolding isn’t just a process leap—it’s a paradigm shift in chip design, achieving 1.4nm-equivalent density via 3D logic stacking and signal-path optimization without EUV. This forces EDA tools, advanced packaging, and domestic photoresists to rapidly co-evolve, creating a design-led manufacturing feedback loop. Compliance-wise, while bypassing lithography bans, reliance on U.S.-origin IP or EDA still exposes secondary sanction risks, accelerating Huawei’s full tech decoupling. Competitively, TSMC (Taiwan, China) may fast-track post-2nm GAA adoption, while NVIDIA could rethink AI interconnect architectures to counter Huawei Ascend’s power-efficiency surge. Within 18 months, SMIC will likely absorb non-EUV-compatible designs at scale, pivoting China’s semiconductor strategy from ‘process chasing’ to ‘architecture defining’—the first credible crack in Moore’s Law hegemony.