Japanese chipmaker Rapidus to offer lower wafer pricing than TSMC — 2nm class silicon to be priced around $20,000 on 2027 launch - Tom's Hardware

Japanese chipmaker Rapidus plans to launch its 2nm fabrication process in 2027, offering wafer pricing significantly below that of TSMC. With quotes ranging from ¥3 million to ¥3.5 million per wafer (... Read original →

Rapidus’s $20K 2nm wafer pricing isn’t just undercutting—it’s a geopolitical play to revive Japan’s semiconductor sovereignty. Technically, its single-wafer flow may speed up cycles, but without an ecosystem like TSMC’s OIP, customers face steep migration costs and yield uncertainty. Downstream, design houses risk delays if they switch solely on price. Geopolitically, heavy Japanese subsidies are offset by tightening EUV export controls and trilateral (U.S.-Japan-Netherlands) supply chain scrutiny, inflating compliance overhead. TSMC will likely ignore price pressure and instead lock in North American clients via A16 ramp; Samsung and Intel may pivot to SF2/N2X differentiation. Within 18 months, if Rapidus fails to prove yield stability and secure anchor clients, its low-price gambit could backfire—turning fabs into stranded assets. The real barrier in advanced nodes is no longer lithography alone, but integrated ecosystem dominance.