Linux 7.2 RISC-V Reduces Kernel Startup Overhead, Eswin SoC Support By Default - Phoronix

The Linux 7.2 kernel development cycle introduced significant enhancements for the RISC-V architecture, including optimizations to reduce kernel startup overhead and default support for Eswin SoCs, pa... Read original →

Linux 7.2’s RISC-V boot-time optimizations—particularly link-time sorting of __mcount_loc to streamline ftrace initialization—are far more than code hygiene; they ripple across toolchains and performance validation stacks. Compilers must adapt symbol handling, while BSP vendors gain tighter boot latency for edge AI and industrial control. Eswin’s default SoC support signals silicon maturity but deepens reliance on SiFive’s P550 ecosystem. Amid U.S.-China tech decoupling, Chinese RISC-V firms risk 'open-source autonomy with hardware dependency' if they can’t establish independent validation beyond reference boards. ARM and Intel will likely counter by tightening RTOS or UEFI ecosystems around their architectures. Over the next 18 months, RISC-V’s shift from 'usable' to 'preferred' hinges on delivering verifiable performance in server/HPC—not just policy tailwinds.