Post-silicon era gets closer as industry giants crack the 2D transistor scaling bottleneck with breakthrough tech — imec, ASML, and TSMC fab complementary 2D-material transistors at 50nm pitch on a 300mm wafer - Tom's Hardware

imec, ASML, and TSMC have achieved a significant breakthrough in 2D transistor technology, demonstrating complementary n- and p-type transistors with atomically thin channels on a 300mm wafer at a 50n... Read original →

The demonstration of 50nm-pitch complementary 2D transistors on 300mm wafers by imec, ASML, and TSMC isn’t a lab curiosity—it’s a paradigm shift. Technologically, it forces co-evolution of EUV patterning, atomic-scale deposition, and wafer-scale transfer, with the reverse TFT flow redefining backend integration. Geopolitically, if U.S. export controls expand to 2D-material tools, non-U.S. foundries face higher validation costs and supply-chain fragmentation. Competitively, Samsung and Intel will rush CFET timelines, but without ASML’s deep EUV co-optimization, replication remains unlikely. Over the next 12–24 months, expect a surge in hybrid 'quasi-2D' devices—silicon GAA channels spliced with 2D materials—to capture early-mover advantage, though true volume production won’t materialize before 2030. Moore’s Law now hinges not on shrinking features, but on dimensional material leaps.